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Graphics Interchange Format  |  1997-10-26  |  60.9 KB  |  561x390  |  4-bit (15 colors)
   ocr: Table 1. BERT mechanisms and implementations. Mechanisms used Branch Block Commercial speculaiive range siz0 implementation Technique execution reduction increase examples Eager execulion 8h 360/91, Sus SuperSpare Disjoint eager oxecution alone with minimal control depencencles (MCD) Single path Rol branch prediction Intel 8086 Static Aiways not taken Inteli 1405 Always taken Sur SuperSparc Sackward Taken: Forward Not Taken (BTEN) - HPPA-7X00 Semistalic profiling) Eariy PowerPCs Dynamic 3-bit DEC. Alpha 21084, AMD-K5 2-bit NexGen 586, PowerPC 604, Cyrix 6x86, Cyrix M2, Aips R11000 Two-levelada ...